Phase lock loop (PLL) circuits are typically used to provide or generate a clock signal that is an integer fraction or integer multiple of a crystal oscillator reference frequency.
FIG. 1 illustrates a conventional phase lock loop architecture. A reference clock 22 generates a reference clock signal having a reference frequency, and the reference clock signal may be coupled with a phase/frequency detector 24 which may be coupled with a low pass filter 26. The output of the low pass filter 26, which is typically a voltage that is proportional to the reference frequency of the clock signal, is coupled with a voltage controlled oscillator 28. The output of VCO 28 can be fed back and divided down in frequency (by M) by feedback divider 30 which provides a divided down feedback signal to the phase/frequency detector 24. The output of the voltage controlled oscillator is an oscillating signal which may be divided down (by N) in frequency by divider 32 in order to provide an oscillating signal having an output frequency.
The dividers 30, 32 are arranged to multiply or divide an circuit's reference frequency. In this way, a phase lock loop 20 can provide a wide range of output frequencies derived from the reference clock. The output frequency of a conventional crystal oscillator and PLL circuit, such as in FIG. 1, is shown in Equation 1.
                              f          Out                =                              M            N                    ⁢                      f            Ref                                              (                  Equation          ⁢                                          ⁢          1                )            
In Equation 1, fOut is the frequency of the output clock from divider 32 and fRef is the frequency of the input reference clock 22.
While a conventional phase locked loop 20 provides a wide range of flexibility in design for use in circuit applications that have different frequency requirements, a conventional phase lock loop circuit can consume a large amount of area on an integrated circuit and may also utilize significant amounts of power.
As recognized by the present inventor, it would be desirable to have a solution that can provide frequency multiplication of a reference clock frequency using a circuit that is small and requires low power when compared with a conventional phase lock loop circuit.
Accordingly, as recognized by the present inventor, what is needed is a frequency multiplication circuit that can provide an alternative design to a conventional phase lock loop circuit.
It is against this background that various embodiments of the present invention were developed.